Jobs at Djinni

About the Role:

We are seeking a motivated Junior Verification Engineer to join our VLSI design and verification team.

This is an excellent opportunity for new graduates with strong academic training in digital design, verification methodologies, and SystemVerilog/UVM.

Responsibilities:

Develop and execute verification testbenches using Verilog/SystemVerilog and UVM

Implement functional and constrained-random tests for block-level and SoC-level designs

Create coverage models (functional, code, assertion-based) and drive coverage closure

Debug simulation failures, interface mismatches, and RTL issues

Write and maintain scoreboards, monitors, agents, drivers, and checkers in UVM

Review design specifications, extract test requirements, and build verification plans

Run regressions, triage failures, and document results

Collaborate closely with RTL designers, DFT, backend, and system architects

Required Qualifications:

B.Sc. or M.Sc. in Electrical/Computer Engineering or related field

Strong academic background in digital logic, computer architecture, and VLSI design

Hands-on experience with Verilog and SystemVerilog (labs, projects, internship)

Basic understanding of UVM methodology

Familiarity with simulation tools (VCS, QuestaSim, Xcelium or similar)

Ability to read and understand RTL code

Good analytical and debugging skills

Strong motivation to grow in advanced functional verification

Nice-to-Have Skills:

Coursework or project experience with UVM testbench development

Familiarity with assertion-based verification (SVA)

Basic scripting (Python, Perl, Shell, TCL)

Experience with coverage-driven verification

Exposure to SoC-level interfaces (AXI, PCIe, DDR, Ethernet, SPI, I2C)

What We Offer:

Full training in modern verification methodologies (UVM, SVA, CRV)

Work with cutting-edge IPs and SoC architectures

Mentorship from senior verification and architecture teams

Clear growth path toward UVM specialist, verification lead, or architect

We are looking for a junior backend VLSI engineer to join our Physical Design team.

This role is ideal for new graduates with strong academic foundations in digital design and VLSI who want to learn and execute a full RTL→GDSII implementation flow using Synopsys tools.

You will gain hands-on experience working on advanced semiconductor technologies, including nodes down to 7 nm, 5 nm, 3 nm, and 2 nm.

Responsibilities:

Assist in synthesis (Design Compiler / Fusion Compiler) from RTL to gate-level netlist

Support floorplanning, power planning, and clock tree design

Perform place and route (P&R) using ICC2 / Fusion Compiler

Contribute to timing analysis and closure using PrimeTime (STA)

Run physical verification checks: DRC, LVS, antenna, IR-drop, EM

Prepare and validate design constraints (SDC, clock definitions, I/O timing)

Help generate and validate physical deliverables (LEF/DEF, SPEF, SDF)

Collaborate with RTL, DFT, package, verification, and integration teams

Document design steps, results, and signoff data

Required Qualifications:

B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or related field

Strong understanding of digital logic, synchronous design, and timing fundamentals

Academic exposure to VLSI backend flows

Basic familiarity with: synthesis, place & route, STA

Scripting skills (TCL, Python, Shell)

Strong analytical and problem-solving mindset

Motivation to learn deep-submicron implementation techniques (FinFET and GAA nodes)

Nice-to-Have Skills

Exposure to Synopsys tools (DC, ICC2, PT) through coursework or projects

Understanding of setup/hold timing, OCV, derates, clock uncertainty

Basic knowledge of physical effects: congestion, crosstalk, IR-drop, EM

Linux environment experience

Familiarity with Git or similar tools

What We Offer:

Hands-on work on advanced semiconductor nodes down to 2 nm

Full training in modern RTL→GDSII physical design flows

Mentorship from senior PD and STA engineers

Opportunity to work on high-performance ASICs and SoC designs

Clear growth path toward P&R specialist, STA engineer, PD lead, or chip integration engineer

About the Role:

We are seeking a motivated Junior Package Engineer with PCB design experience to join our IC packaging and signal/power integrity team.

You will support the development of advanced semiconductor packages and perform SI/PI analysis for high-speed interfaces such as Ethernet, PCIe, DDR, and SerDes.

Responsibilities:

• Assist in IC package design (substrate layout, stack-up, routing, DRC checks)
• Support package floorplanning and die/ball map development
• Work with senior engineers to run SI simulations (S-parameters, insertion loss, eye diagrams)
• Perform PI/PDN analysis (IR drop, decap planning, impedance profiles)
• Translate PCB experience into package-level routing constraints (differential pair rules, impedance control)
• Help model high-speed interfaces: Ethernet, PCIe, DDR, SerDes
• Collaborate with silicon, system, and PCB teams on end-to-end interconnect design
• Document design guidelines, simulation results, and engineering reports

Required Qualifications:

• Experience with PCB design tools (Altium, OrCAD, Allegro, KiCad, or similar)
• Understanding of high-speed differential routing and board-level signal integrity basics
• Familiarity with impedance control, vias, stackups, return paths, PDN concepts
• Exposure to interfaces such as Ethernet, PCIe, DDR
• Basic scripting or automation skills (Python/Matlab preferred)
• Strong problem-solving abilities and attention to detail
• High motivation to learn package design and SI/PI methodologies
• Nice-to-Have Skills
• Familiarity with package design tools: Cadence SIP/APD, Xpeedic, Mentor Xpedition
• Exposure to SI/PI simulation tools: ANSYS SIwave, HFSS, Sigrity, ADS
• Understanding of flip-chip, BGA, RDL, 2.5D/3D packaging

• Knowledge of SerDes, USB, LPDDR, or high-speed PHY design principles

   

What We Offer: 

• Full training in IC packaging, SI/PI analysis, and advanced interconnect design
• Opportunity to work with cutting-edge technologies (PCIe Gen5/6, DDR5/6, chiplets)
• Mentorship from senior package, SI, and system engineers
• A clear growth path toward package architect, SI/PI lead, or chiplet interconnect specialist

We are looking for highly motivated junior engineers to join our Design-for-Test (DFT) team.

This is an excellent opportunity for graduates who want to build expertise in Scan, Memory BIST, and JTAG within advanced VLSI development.

Responsibilities:

Learn and support implementation of scan insertion and scan chain architecture

Assist in ATPG pattern generation and test coverage analysis

Participate in Memory BIST (MBIST) integration and verification

Work with JTAG / IEEE 1149.1 boundary scan concepts and flows

Help debug test-related issues at RTL and gate level

Collaborate with senior DFT engineers on SoC-level test strategy

Required Background:

Academic knowledge in digital logic, VLSI design, and computer architecture

Basic familiarity with DFT concepts: scan, ATPG, BIST, boundary scan

Understanding of Verilog or VHDL

Scripting basics (Python, TCL, Shell)

Good analytical and problem-solving skills

Strong motivation to learn industry-standard DFT tools and flows

What We Offer:

Full training in Scan, MBIST, JTAG, ATPG, and DFT methodologies

Mentorship by experienced DFT engineers

Exposure to advanced SoC development flows and signoff

Growth path toward senior DFT, test architecture, or silicon bring-up roles

About the Role:

We are seeking a motivated Junior Package Engineer with PCB design experience to join our IC packaging and signal/power integrity team.

You will support the development of advanced semiconductor packages and perform SI/PI analysis for high-speed interfaces such as Ethernet, PCIe, DDR, and SerDes.

Responsibilities:

• Assist in IC package design (substrate layout, stack-up, routing, DRC checks)
• Support package floorplanning and die/ball map development
• Work with senior engineers to run SI simulations (S-parameters, insertion loss, eye diagrams)
• Perform PI/PDN analysis (IR drop, decap planning, impedance profiles)
• Translate PCB experience into package-level routing constraints (differential pair rules, impedance control)
• Help model high-speed interfaces: Ethernet, PCIe, DDR, SerDes
• Collaborate with silicon, system, and PCB teams on end-to-end interconnect design
• Document design guidelines, simulation results, and engineering reports

Required Qualifications:

• Experience with PCB design tools (Altium, OrCAD, Allegro, KiCad, or similar)
• Understanding of high-speed differential routing and board-level signal integrity basics
• Familiarity with impedance control, vias, stackups, return paths, PDN concepts
• Exposure to interfaces such as Ethernet, PCIe, DDR
• Basic scripting or automation skills (Python/Matlab preferred)
• Strong problem-solving abilities and attention to detail

• High motivation to learn package design and SI/PI methodologies

   

  Nice-to-Have Skills

• Familiarity with package design tools: Cadence SIP/APD, Xpeedic, Mentor Xpedition
• Exposure to SI/PI simulation tools: ANSYS SIwave, HFSS, Sigrity, ADS
• Understanding of flip-chip, BGA, RDL, 2.5D/3D packaging

• Knowledge of SerDes, USB, LPDDR, or high-speed PHY design principles

   

What We Offer: 

• Full training in IC packaging, SI/PI analysis, and advanced interconnect design
• Opportunity to work with cutting-edge technologies (PCIe Gen5/6, DDR5/6, chiplets)
• Mentorship from senior package, SI, and system engineers
• A clear growth path toward package architect, SI/PI lead, or chiplet interconnect specialist

About the Role:

We are seeking a motivated Junior Package Engineer with PCB design experience to join our IC packaging and signal/power integrity team.

You will support the development of advanced semiconductor packages and perform SI/PI analysis for high-speed interfaces such as Ethernet, PCIe, DDR, and SerDes.

Responsibilities:

• Assist in IC package design (substrate layout, stack-up, routing, DRC checks)
• Support package floorplanning and die/ball map development
• Work with senior engineers to run SI simulations (S-parameters, insertion loss, eye diagrams)
• Perform PI/PDN analysis (IR drop, decap planning, impedance profiles)
• Translate PCB experience into package-level routing constraints (differential pair rules, impedance control)
• Help model high-speed interfaces: Ethernet, PCIe, DDR, SerDes
• Collaborate with silicon, system, and PCB teams on end-to-end interconnect design
• Document design guidelines, simulation results, and engineering reports

Required Qualifications:

• Experience with PCB design tools (Altium, OrCAD, Allegro, KiCad, or similar)
• Understanding of high-speed differential routing and board-level signal integrity basics
• Familiarity with impedance control, vias, stackups, return paths, PDN concepts
• Exposure to interfaces such as Ethernet, PCIe, DDR
• Basic scripting or automation skills (Python/Matlab preferred)
• Strong problem-solving abilities and attention to detail

• High motivation to learn package design and SI/PI methodologies

   

  Nice-to-Have Skills

• Familiarity with package design tools: Cadence SIP/APD, Xpeedic, Mentor Xpedition
• Exposure to SI/PI simulation tools: ANSYS SIwave, HFSS, Sigrity, ADS
• Understanding of flip-chip, BGA, RDL, 2.5D/3D packaging

• Knowledge of SerDes, USB, LPDDR, or high-speed PHY design principles

   

What We Offer: 

• Full training in IC packaging, SI/PI analysis, and advanced interconnect design
• Opportunity to work with cutting-edge technologies (PCIe Gen5/6, DDR5/6, chiplets)
• Mentorship from senior package, SI, and system engineers
• A clear growth path toward package architect, SI/PI lead, or chiplet interconnect specialist

We design integrated circuits for consumer, medical and automotive markets. The majority of these designs are complex SoC/ASIC architectures that integrate IPs, such as ARM and RISC-V CPUs and peripherals, DSP cores, analog cells and other IPs with progressive technology nodes: 24, 10, 7,  3 nanometers.

In our daily work we constantly face challenges that requires out of box thinking. This makes our lives an interesting and challenging adventure. Such attitude permits creation of products full of features that often outperform market. We are constant learners, the same we expect from our new employees. Hence, we’d be happy to meet passionate and keen on learning, bright young individuals.

Below is a brief list of skills/knowledge that ideally suit our job profile. Still it’s not an issue if you don’t possess some of those. To our opinion the fundamental engineer’s skills are problem solving and ability to learn.

Desired knowledge you may possess:

• Good understanding of digital/analog electronics and semiconductors physics
• FPGA placement and routing using EDA tools
• Experience with PCB design using such tools such as OrCAD, Altium Designer or similar
• Basic knowledge of scripting languages such as Tcl, Python, Make
• Beginner’s level of English

Optional skills you may have:

• FPGA design using HDLs or schematics editor
• Embedded systems design using IDEs such as Keil, AtmelStudio, IAR

We offer:

• Part- or full-time employment, flexible schedule
• On-job training in our Kyiv office with high skilled professionals
• Potential growth in the direction of ASIC design
• Paid sick leave and vacation

We design integrated circuits for consumer, medical and automotive markets. The majority of these designs are complex SoC/ASIC architectures that integrate IPs, such as ARM and RISC-V CPUs and peripherals, DSP cores, analog cells and other IPs with progressive technology nodes: 14, 10, 8, 7 nanometers.

You will be responsible for digital logic design and verification. Besides, you'd be able to learn and improve related methodologies. Below is a brief list of skills/knowledge that ideally suit our job profile. Still it’s not an issue if you don’t possess some of those. To our opinion the fundamental engineer’s skills are analytical thinking and ability to learn.

Essential qualifications:

-Degree in Electronics or related fields

-Good understanding of digital electronics

-Experience with EDA tools (Xilinx, Mentor Graphics, Synopsys or similar)

-Beginner’s level of English or higher

Optional qualifications you may have:

-FPGA design using HDL (Verilog, VHDL) or schematics editor

-IC design verification using System Verilog

-CPU architecture knowledge, embedded SW development

We offer:

-Full-time employment, flexible schedule

-On-job training in our Kyiv office with high skilled professionals

-Potential growth in directions of ASIC/FPGA design

-Social benefits, modern and comfortable office facilities

We design integrated circuits for consumer, medical and automotive markets. The majority of these designs are complex SoC/ASIC architectures that integrate IPs, such as ARM and RISC-V CPUs and peripherals, DSP cores, analog cells and other IPs with progressive technology nodes: 24, 10, 7,  3 nanometers.

In our daily work we constantly face challenges that requires out of box thinking. This makes our lives an interesting and challenging adventure. Such attitude permits creation of products full of features that often outperform market. We are constant learners, the same we expect from our new employees. Hence, we’d be happy to meet passionate and keen on learning, bright young individuals.

Below is a brief list of skills/knowledge that ideally suit our job profile. Still it’s not an issue if you don’t possess some of those. To our opinion the fundamental engineer’s skills are problem solving and ability to learn.

Desired knowledge you may possess:

• Good understanding of digital/analog electronics and semiconductors physics
• FPGA placement and routing using EDA tools
• Experience with PCB design using such tools such as OrCAD, Altium Designer or similar
• Basic knowledge of scripting languages such as Tcl, Python, Make
• Beginner’s level of English

Optional skills you may have:

• FPGA design using HDLs or schematics editor
• Embedded systems design using IDEs such as Keil, AtmelStudio, IAR

We offer:

• Part- or full-time employment, flexible schedule
• On-job training in our Kyiv office with high skilled professionals
• Potential growth in the direction of ASIC design
• Paid sick leave and vacation

Responsibilities

• Setting up a central Kafka instance
• Configuring and managing message brokers (Kafka)
• Operating and scaling Kafka-based systems
• Security hardening and performance optimization

Core Skills

• Deep, multi-year hands-on Kafka experience
• Strong background in configuring Kafka environments
• Experience managing message broker services
• Security, scaling & operational expertise
• Optional: Experience in AWS Cloud operations

Project Details
Start: ASAP
Workload: Full-time
Duration: 5–6 months
Location: Remote (EU)!!!
Project Language: English

Responsibilities:
Further development of a custom-built web application
Performance optimization and modernization of backend architecture
Refactoring existing .NET components (.NET 9)
Full-stack development with React & ASP.NET Core
Collaboration within an agile Scrum environment

Core Skills:
C#, ASP.NET Core (.NET 9), containerized deployments, Linux (Azure AKS)
React 16.14, Redux/Flux, TypeScript
Azure SQL, SSRS/PowerBI, SSIS
GitLab CI/CD, SonarQube

Qualifications:
Strong full-stack experience
Excellent knowledge of backend architecture and performance tuning
Practical experience with Azure environments
Solid experience with React frontends

Project Details: 
Start: ASAP
Workload: Full Time
Duration: 3 MM ++
Location: Remote (EU) !!!
Project Language: English

Project Duration: April 13, 2026 – June 30, 2026
Location: Remote (Poland)
Experience Required: 7+ years

About the Role
We are seeking an experienced UX Designer specializing in Digital Employee Experience to design intuitive, modern intranet and internal communication platforms based on Microsoft SharePoint Online and Microsoft Viva. The role focuses on transforming research insights into user flows, navigation systems, and interactive concepts, while contributing to early-stage product vision and proof-of-concept development.

Key Responsibilities

• Lead UX discovery phases and develop concepts for employee-facing platforms and intranet solutions
• Design information architecture, navigation systems, and user journeys tailored to enterprise users
• Create wireframes, prototypes, and high-fidelity designs aligned with SharePoint and Viva UX standards
• Collaborate with solution architects to ensure feasibility across Microsoft Viva (Connections, Engage, Amplify), Microsoft Teams, and Microsoft Copilot
• Design dashboards, landing pages, and role-based content experiences
• Support personalization strategies, including audience targeting, metadata, and content structuring
• Conduct usability testing and iterate on designs based on feedback
• Work closely with engineering, content, and product teams to align UX with technical and business requirements

Requirements (Must Have)

• 7+ years of experience in UX design
• Proven experience designing enterprise portals, intranets, or internal communication tools
• Strong expertise in information architecture, prototyping, wireframing, and UX research
• Hands-on experience with Microsoft 365 ecosystem, including SharePoint Online and Viva
• Understanding of employee journey mapping and accessibility-first design principles
• Experience collaborating with cross-functional teams (engineering, content, product)
• Fluent English communication skills

Nice to Have

• Experience with SharePoint design systems, component libraries, and Viva UX patterns
• Familiarity with adaptive cards, Microsoft Teams UI, or Copilot-based workflows
• Proficiency with design tools such as Figma, Sketch, or Adobe XD
• Experience working in Agile environments or complex multi-stream programs

Core Technologies
UX Design, Microsoft Office 365, SharePoint

Tasks:

• Design and implementation of scalable hub-and-spoke data architectures
• Processing and analysis of large datasets in Google Cloud (BigQuery)
• Development and optimization of ETL/ELT pipelines (including CDC and SCD Type 1/2)
• Building near real-time data pipelines
• Implementation of infrastructure as code (Terraform)
• Ensuring data quality, performance, and scalability
• Collaboration with data and platform teams

Requirements:

• 3–5 years of experience as a Data Engineer or in a similar role
• Strong expertise in:
• Google Cloud (BigQuery)
• SQL and Dataform
• ETL/ELT processes (CDC, SCD Type 1/2)
• Experience with:
• Terraform (Infrastructure as Code)
• Streaming technologies (Pub/Sub, Dataflow, Apache Beam)
• Python and ideally Java
• Experience handling large datasets and cloud-based architectures
• Structured and independent working style

 Project details:

• Start: April 2026
• Duration: 6 months
• Workload: Full-time
• Location: 100% remote

InsulaLabs is an international IT company that helps product and technology businesses scale their engineering teams and launch service solutions through outstaffing and outsourcing models.

We are currently transitioning from a classic staff augmentation approach to a more mature solution and delivery model. This transformation is why we are strengthening the company’s technical core.

We are looking for a Technical Delivery Lead — a hands-on technical leader who will take ownership of technical expertise, validation, presales, and delivery quality.

This is not a theoretical role and not pure management.
It is a role for an expert, validator, and result-driven leader.
 

Responsibilities:

• Validate candidates and engineers
• Conduct and oversee technical interviews
• Participate in performance reviews (technical evaluation)
• Create and support Personal Development Plans (PDPs)
• Assess real-world performance of engineers at client projects
• Participate in technical presales
• Estimate scope, timelines, and required resources
• Support Sales in setting realistic client expectations
• Maintain strong business impact awareness
• Lead technical project kick-offs after deal closure
• Maintain a delivery risk radar and ensure alignment with agreements
• Identify risks early and proactively
• Control delivery quality across teams and partners
   

Requirements

• 8+ years in IT 
• Background as Tech Lead, Engineering Manager, or Technical Delivery Lead
• Broad technical expertise (Frontend, Backend, QA, DevOps)
• Presale and estimation experience
• Strong systems thinking
• Ability to translate technical decisions into business language
• Ownership mindset and results orientation
• English proficiency: C1
   

What We Offer

• Fully remote work format
• Direct collaboration with Executives and key clients
• Influence on company strategy and growth through 2026
• Competitive compensation (discussed individually)
• Opportunity to evolve into Head of Technical Delivery or CTO
   

Why This Role Matters

You will build the technical foundation of Insula Labs, not just maintain processes. This role has real impact on business results, delivery quality, company reputation, and long-term growth.

We’re looking for a proactive and genuinely passionate Motion Designer who’s eager to grow, stay on top of design trends, and bring creative energy to our projects. You’ll become a part of our fun yet expert team, where we value curiosity, initiative, and collaboration just as much as technical skill.

Key Skills:

• Quickly create video creatives and promotional content for advertising campaigns.
• Stay updated on motion graphics, marketing design trends, and new AI tools, and share insights with the team.
• Flexibility and ability to quickly learn new tools and processes, and immediately apply them in work.
• Proactivity, autonomy, and ability to take responsibility and propose solutions.

Technical Requirements:

• Proficiency in Adobe After Effects.
• Basic knowledge of Adobe Photoshop, Premiere Pro, Illustrator, and Figma.
• Understanding of generative AI tools and their use in image or video generation for specific tasks.

Nice to Have:

• Experience in advertising creatives, especially for social media and digital campaigns.
• Experience in creative production and marketing for the Health & Fitness industry.
• Deep knowledge of generative AI tools and interfaces (e.g., ComfyUI or similar platforms).