Jobs at Djinni

We are building a next-generation ecosystem of corporate solutions. Our team is focused on deep automation and the development of custom components that truly transform the user experience within SharePoint Online and Power Platform. If you know how to turn standard Microsoft tools into powerful business engines—we are looking for you!

What you will do:

• Develop SPFx web parts and extensions using React.
• Build complex Model-driven and Canvas apps leveraging Dataverse.
• Work with Microsoft Graph and external REST APIs.
• Implement AI capabilities via AI Builder, Copilot Studio, and Azure OpenAI Service.

• Manage Application Lifecycle Management (ALM) and solution deployment across environments.

   

Our Ideal Candidate:

• Has 3–4+ years of commercial development experience.
• Expertly commands JavaScript / TypeScript and React.
• Deeply understands M365 architecture and Dataverse capabilities.

• Communicates fluently in English (Upper-Intermediate level) for international collaboration.

   

Bonus Points if you:

• Have experience with PnP JS or Power Apps Component Framework (PCF).
• Configured CI/CD pipelines in Azure DevOps.

• Have worked with Azure Functions or Logic Apps.

   

Taurus Quadra is a software development company focused on the planning, design, implementation and migration of SharePoint/Office365. With more than 25 SharePoint-based projects in the US, Europe and Ukraine, Taurus Quadra has the experience, expertise and integration capabilities to build, extend, integrate or implement corporate portals, business apps and Mobile Applications Development (Android, IOS, Windows).

Summary

ChargeAutomation is a payment automation platform built for short-term rental operators. We help property managers get paid faster, reduce payment friction, and deliver better guest experiences, from booking to checkout. We’re remote-first, async-first, and growing fast.


What you’ll do:
- Own the full outbound sales pipeline, from lead sourcing to closed deal
- Build and run cold outreach sequences targeting property managers and STR operators across EMEA.
- Source and qualify leads using Apollo, Instantly, and LinkedIn
- Run discovery calls, product demos, and handle objections with operators who manage 10–500+ rental units
- Hit and exceed monthly pipeline and revenue targets

- Collaborate async with marketing and product to sharpen messaging and ICP targeting
- Report on pipeline health, conversion metrics, and deal velocity

What you bring:
* 3–5 years in SaaS sales or hospitality with a consistent track record (no job-hopping)
* Real outbound experience you’ve personally built cold outreach sequences and can show the results
* Comfortable with MRR, ARR, churn, LTV, CAC, and pipeline math
* Fluent English — written and spoken — and confident on video calls
* Prior remote work experience (2+ years preferred)
* CRM proficiency (HubSpot, Salesforce, or Pipedrive)
* Experience in the short-term rental / vacation rental / PropTech space
* Familiarity with Apollo, Instantly, Outreach, or Salesloft
* Second language is a plus (Spanish, Portuguese, German, or French)
* SaaS OR hospitality experience (highly valued)


Why ChargeAutomation
* You’re shaping how we sell, not following a playbook someone else wrote
* A vertical that’s exploding, short-term rentals are a $100B+ market with massive payment friction to solve
* Remote-first, async-first. No micromanagement, no pointless standups, just results
* A team that’s direct, fast, and fun

We are looking for a junior backend VLSI engineer to join our Physical Design team.

This role is ideal for new graduates with strong academic foundations in digital design and VLSI who want to learn and execute a full RTL→GDSII implementation flow using Synopsys tools.

You will gain hands-on experience working on advanced semiconductor technologies, including nodes down to 7 nm, 5 nm, 3 nm, and 2 nm.

Responsibilities:

Assist in synthesis (Design Compiler / Fusion Compiler) from RTL to gate-level netlist

Support floorplanning, power planning, and clock tree design

Perform place and route (P&R) using ICC2 / Fusion Compiler

Contribute to timing analysis and closure using PrimeTime (STA)

Run physical verification checks: DRC, LVS, antenna, IR-drop, EM

Prepare and validate design constraints (SDC, clock definitions, I/O timing)

Help generate and validate physical deliverables (LEF/DEF, SPEF, SDF)

Collaborate with RTL, DFT, package, verification, and integration teams

Document design steps, results, and signoff data

Required Qualifications:

B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or related field

Strong understanding of digital logic, synchronous design, and timing fundamentals

Academic exposure to VLSI backend flows

Basic familiarity with: synthesis, place & route, STA

Scripting skills (TCL, Python, Shell)

Strong analytical and problem-solving mindset

Motivation to learn deep-submicron implementation techniques (FinFET and GAA nodes)

Nice-to-Have Skills

Exposure to Synopsys tools (DC, ICC2, PT) through coursework or projects

Understanding of setup/hold timing, OCV, derates, clock uncertainty

Basic knowledge of physical effects: congestion, crosstalk, IR-drop, EM

Linux environment experience

Familiarity with Git or similar tools

What We Offer:

Hands-on work on advanced semiconductor nodes down to 2 nm

Full training in modern RTL→GDSII physical design flows

Mentorship from senior PD and STA engineers

Opportunity to work on high-performance ASICs and SoC designs

Clear growth path toward P&R specialist, STA engineer, PD lead, or chip integration engineer

About the Role:

We are seeking a motivated Junior Package Engineer with PCB design experience to join our IC packaging and signal/power integrity team.

You will support the development of advanced semiconductor packages and perform SI/PI analysis for high-speed interfaces such as Ethernet, PCIe, DDR, and SerDes.

Responsibilities:

• Assist in IC package design (substrate layout, stack-up, routing, DRC checks)
• Support package floorplanning and die/ball map development
• Work with senior engineers to run SI simulations (S-parameters, insertion loss, eye diagrams)
• Perform PI/PDN analysis (IR drop, decap planning, impedance profiles)
• Translate PCB experience into package-level routing constraints (differential pair rules, impedance control)
• Help model high-speed interfaces: Ethernet, PCIe, DDR, SerDes
• Collaborate with silicon, system, and PCB teams on end-to-end interconnect design
• Document design guidelines, simulation results, and engineering reports

Required Qualifications:

• Experience with PCB design tools (Altium, OrCAD, Allegro, KiCad, or similar)
• Understanding of high-speed differential routing and board-level signal integrity basics
• Familiarity with impedance control, vias, stackups, return paths, PDN concepts
• Exposure to interfaces such as Ethernet, PCIe, DDR
• Basic scripting or automation skills (Python/Matlab preferred)
• Strong problem-solving abilities and attention to detail
• High motivation to learn package design and SI/PI methodologies
• Nice-to-Have Skills
• Familiarity with package design tools: Cadence SIP/APD, Xpeedic, Mentor Xpedition
• Exposure to SI/PI simulation tools: ANSYS SIwave, HFSS, Sigrity, ADS
• Understanding of flip-chip, BGA, RDL, 2.5D/3D packaging

• Knowledge of SerDes, USB, LPDDR, or high-speed PHY design principles

   

What We Offer: 

• Full training in IC packaging, SI/PI analysis, and advanced interconnect design
• Opportunity to work with cutting-edge technologies (PCIe Gen5/6, DDR5/6, chiplets)
• Mentorship from senior package, SI, and system engineers
• A clear growth path toward package architect, SI/PI lead, or chiplet interconnect specialist

About the Role:

We are seeking a motivated Junior Verification Engineer to join our VLSI design and verification team.

This is an excellent opportunity for new graduates with strong academic training in digital design, verification methodologies, and SystemVerilog/UVM.

Responsibilities:

Develop and execute verification testbenches using Verilog/SystemVerilog and UVM

Implement functional and constrained-random tests for block-level and SoC-level designs

Create coverage models (functional, code, assertion-based) and drive coverage closure

Debug simulation failures, interface mismatches, and RTL issues

Write and maintain scoreboards, monitors, agents, drivers, and checkers in UVM

Review design specifications, extract test requirements, and build verification plans

Run regressions, triage failures, and document results

Collaborate closely with RTL designers, DFT, backend, and system architects

Required Qualifications:

B.Sc. or M.Sc. in Electrical/Computer Engineering or related field

Strong academic background in digital logic, computer architecture, and VLSI design

Hands-on experience with Verilog and SystemVerilog (labs, projects, internship)

Basic understanding of UVM methodology

Familiarity with simulation tools (VCS, QuestaSim, Xcelium or similar)

Ability to read and understand RTL code

Good analytical and debugging skills

Strong motivation to grow in advanced functional verification

Nice-to-Have Skills:

Coursework or project experience with UVM testbench development

Familiarity with assertion-based verification (SVA)

Basic scripting (Python, Perl, Shell, TCL)

Experience with coverage-driven verification

Exposure to SoC-level interfaces (AXI, PCIe, DDR, Ethernet, SPI, I2C)

What We Offer:

Full training in modern verification methodologies (UVM, SVA, CRV)

Work with cutting-edge IPs and SoC architectures

Mentorship from senior verification and architecture teams

Clear growth path toward UVM specialist, verification lead, or architect

We are looking for highly motivated junior engineers to join our Design-for-Test (DFT) team.

This is an excellent opportunity for graduates who want to build expertise in Scan, Memory BIST, and JTAG within advanced VLSI development.

Responsibilities:

Learn and support implementation of scan insertion and scan chain architecture

Assist in ATPG pattern generation and test coverage analysis

Participate in Memory BIST (MBIST) integration and verification

Work with JTAG / IEEE 1149.1 boundary scan concepts and flows

Help debug test-related issues at RTL and gate level

Collaborate with senior DFT engineers on SoC-level test strategy

Required Background:

Academic knowledge in digital logic, VLSI design, and computer architecture

Basic familiarity with DFT concepts: scan, ATPG, BIST, boundary scan

Understanding of Verilog or VHDL

Scripting basics (Python, TCL, Shell)

Good analytical and problem-solving skills

Strong motivation to learn industry-standard DFT tools and flows

What We Offer:

Full training in Scan, MBIST, JTAG, ATPG, and DFT methodologies

Mentorship by experienced DFT engineers

Exposure to advanced SoC development flows and signoff

Growth path toward senior DFT, test architecture, or silicon bring-up roles

About the Role:

We are seeking a motivated Junior Package Engineer with PCB design experience to join our IC packaging and signal/power integrity team.

You will support the development of advanced semiconductor packages and perform SI/PI analysis for high-speed interfaces such as Ethernet, PCIe, DDR, and SerDes.

Responsibilities:

• Assist in IC package design (substrate layout, stack-up, routing, DRC checks)
• Support package floorplanning and die/ball map development
• Work with senior engineers to run SI simulations (S-parameters, insertion loss, eye diagrams)
• Perform PI/PDN analysis (IR drop, decap planning, impedance profiles)
• Translate PCB experience into package-level routing constraints (differential pair rules, impedance control)
• Help model high-speed interfaces: Ethernet, PCIe, DDR, SerDes
• Collaborate with silicon, system, and PCB teams on end-to-end interconnect design
• Document design guidelines, simulation results, and engineering reports

Required Qualifications:

• Experience with PCB design tools (Altium, OrCAD, Allegro, KiCad, or similar)
• Understanding of high-speed differential routing and board-level signal integrity basics
• Familiarity with impedance control, vias, stackups, return paths, PDN concepts
• Exposure to interfaces such as Ethernet, PCIe, DDR
• Basic scripting or automation skills (Python/Matlab preferred)
• Strong problem-solving abilities and attention to detail

• High motivation to learn package design and SI/PI methodologies

   

  Nice-to-Have Skills

• Familiarity with package design tools: Cadence SIP/APD, Xpeedic, Mentor Xpedition
• Exposure to SI/PI simulation tools: ANSYS SIwave, HFSS, Sigrity, ADS
• Understanding of flip-chip, BGA, RDL, 2.5D/3D packaging

• Knowledge of SerDes, USB, LPDDR, or high-speed PHY design principles

   

What We Offer: 

• Full training in IC packaging, SI/PI analysis, and advanced interconnect design
• Opportunity to work with cutting-edge technologies (PCIe Gen5/6, DDR5/6, chiplets)
• Mentorship from senior package, SI, and system engineers
• A clear growth path toward package architect, SI/PI lead, or chiplet interconnect specialist

About the Role:

We are seeking a motivated Junior Package Engineer with PCB design experience to join our IC packaging and signal/power integrity team.

You will support the development of advanced semiconductor packages and perform SI/PI analysis for high-speed interfaces such as Ethernet, PCIe, DDR, and SerDes.

Responsibilities:

• Assist in IC package design (substrate layout, stack-up, routing, DRC checks)
• Support package floorplanning and die/ball map development
• Work with senior engineers to run SI simulations (S-parameters, insertion loss, eye diagrams)
• Perform PI/PDN analysis (IR drop, decap planning, impedance profiles)
• Translate PCB experience into package-level routing constraints (differential pair rules, impedance control)
• Help model high-speed interfaces: Ethernet, PCIe, DDR, SerDes
• Collaborate with silicon, system, and PCB teams on end-to-end interconnect design
• Document design guidelines, simulation results, and engineering reports

Required Qualifications:

• Experience with PCB design tools (Altium, OrCAD, Allegro, KiCad, or similar)
• Understanding of high-speed differential routing and board-level signal integrity basics
• Familiarity with impedance control, vias, stackups, return paths, PDN concepts
• Exposure to interfaces such as Ethernet, PCIe, DDR
• Basic scripting or automation skills (Python/Matlab preferred)
• Strong problem-solving abilities and attention to detail

• High motivation to learn package design and SI/PI methodologies

   

  Nice-to-Have Skills

• Familiarity with package design tools: Cadence SIP/APD, Xpeedic, Mentor Xpedition
• Exposure to SI/PI simulation tools: ANSYS SIwave, HFSS, Sigrity, ADS
• Understanding of flip-chip, BGA, RDL, 2.5D/3D packaging

• Knowledge of SerDes, USB, LPDDR, or high-speed PHY design principles

   

What We Offer: 

• Full training in IC packaging, SI/PI analysis, and advanced interconnect design
• Opportunity to work with cutting-edge technologies (PCIe Gen5/6, DDR5/6, chiplets)
• Mentorship from senior package, SI, and system engineers
• A clear growth path toward package architect, SI/PI lead, or chiplet interconnect specialist

We design integrated circuits for consumer, medical and automotive markets. The majority of these designs are complex SoC/ASIC architectures that integrate IPs, such as ARM and RISC-V CPUs and peripherals, DSP cores, analog cells and other IPs with progressive technology nodes: 24, 10, 7,  3 nanometers.

In our daily work we constantly face challenges that requires out of box thinking. This makes our lives an interesting and challenging adventure. Such attitude permits creation of products full of features that often outperform market. We are constant learners, the same we expect from our new employees. Hence, we’d be happy to meet passionate and keen on learning, bright young individuals.

Below is a brief list of skills/knowledge that ideally suit our job profile. Still it’s not an issue if you don’t possess some of those. To our opinion the fundamental engineer’s skills are problem solving and ability to learn.

Desired knowledge you may possess:

• Good understanding of digital/analog electronics and semiconductors physics
• FPGA placement and routing using EDA tools
• Experience with PCB design using such tools such as OrCAD, Altium Designer or similar
• Basic knowledge of scripting languages such as Tcl, Python, Make
• Beginner’s level of English

Optional skills you may have:

• FPGA design using HDLs or schematics editor
• Embedded systems design using IDEs such as Keil, AtmelStudio, IAR

We offer:

• Part- or full-time employment, flexible schedule
• On-job training in our Kyiv office with high skilled professionals
• Potential growth in the direction of ASIC design
• Paid sick leave and vacation

We design integrated circuits for consumer, medical and automotive markets. The majority of these designs are complex SoC/ASIC architectures that integrate IPs, such as ARM and RISC-V CPUs and peripherals, DSP cores, analog cells and other IPs with progressive technology nodes: 14, 10, 8, 7 nanometers.

You will be responsible for digital logic design and verification. Besides, you'd be able to learn and improve related methodologies. Below is a brief list of skills/knowledge that ideally suit our job profile. Still it’s not an issue if you don’t possess some of those. To our opinion the fundamental engineer’s skills are analytical thinking and ability to learn.

Essential qualifications:

-Degree in Electronics or related fields

-Good understanding of digital electronics

-Experience with EDA tools (Xilinx, Mentor Graphics, Synopsys or similar)

-Beginner’s level of English or higher

Optional qualifications you may have:

-FPGA design using HDL (Verilog, VHDL) or schematics editor

-IC design verification using System Verilog

-CPU architecture knowledge, embedded SW development

We offer:

-Full-time employment, flexible schedule

-On-job training in our Kyiv office with high skilled professionals

-Potential growth in directions of ASIC/FPGA design

-Social benefits, modern and comfortable office facilities

We design integrated circuits for consumer, medical and automotive markets. The majority of these designs are complex SoC/ASIC architectures that integrate IPs, such as ARM and RISC-V CPUs and peripherals, DSP cores, analog cells and other IPs with progressive technology nodes: 24, 10, 7,  3 nanometers.

In our daily work we constantly face challenges that requires out of box thinking. This makes our lives an interesting and challenging adventure. Such attitude permits creation of products full of features that often outperform market. We are constant learners, the same we expect from our new employees. Hence, we’d be happy to meet passionate and keen on learning, bright young individuals.

Below is a brief list of skills/knowledge that ideally suit our job profile. Still it’s not an issue if you don’t possess some of those. To our opinion the fundamental engineer’s skills are problem solving and ability to learn.

Desired knowledge you may possess:

• Good understanding of digital/analog electronics and semiconductors physics
• FPGA placement and routing using EDA tools
• Experience with PCB design using such tools such as OrCAD, Altium Designer or similar
• Basic knowledge of scripting languages such as Tcl, Python, Make
• Beginner’s level of English

Optional skills you may have:

• FPGA design using HDLs or schematics editor
• Embedded systems design using IDEs such as Keil, AtmelStudio, IAR

We offer:

• Part- or full-time employment, flexible schedule
• On-job training in our Kyiv office with high skilled professionals
• Potential growth in the direction of ASIC design
• Paid sick leave and vacation

We are an SEO team focused on developing projects in High-Risk industries. We work with international markets and actively scale link-building strategies through outreach, PR placements, and partner platforms.

We are currently looking for an Outreach Specialist to strengthen our iGaming direction, expand our network of high-quality placements, build relationships with webmasters, and discover new link-building opportunities.

Responsibilities

• Searching for and selecting relevant websites for placements according to SEO specialists’ briefs.
• Communicating with webmasters: negotiations, agreeing on terms and placement costs.
• Preparing briefs for writers to create articles for placements.
• Reviewing completed content for compliance with the brief before submission for publication.
• Organizing and managing the publication process on partner websites.
• Verifying correct placement: links, anchors, dofollow/nofollow attributes, page indexing.
• Adding all placements to Linkchecker and monitoring link status and parameters.
• Maintaining and regularly updating the database of websites (contacts, placement terms, cooperation history).

Requirements

• At least 1 year of experience as an Outreach Specialist in iGaming / High-Risk niches.
• Own database of websites and webmaster contacts is a strong advantage.
• Understanding of link-building and SEO principles (link types, anchors, dofollow/nofollow, indexing, basic site metrics).
• Ability to find and analyze websites based on given criteria (traffic, GEO, relevance, metrics).
• Negotiation and business communication skills with webmasters; English level B1 or higher.
• Attention to detail when checking placements and following briefs.
• Proactivity and independence in finding new websites and placement opportunities.
• Experience with SEO tools (Ahrefs, SimilarWeb, Linkchecker, or similar).
• Ability to structure and maintain a website database (Google Sheets, Notion, CRM, etc.).

What you will appreciate at Flint Group

• A professional growth environment — opportunities to develop expertise in SEO and iGaming, test new approaches, and scale your skills 🚀
• Mentorship and support from experienced SEO specialists and team leaders 🤝
• 18 paid vacation days per year and paid sick leave 🌴
• An open and supportive team culture that values initiative, knowledge sharing, and collaboration 💬

Description

GlobalLogic has been engaged in exploring opportunities to implement ML/AL/GenAI-powered applications for multinational industrial conglomerate since 2023, aiming to enhance business efficiency.

You will be working on projects implying complex data processing pipelines for predictive maintenance anaylitics.

Projects tech stack: Kubernetes, Terraform, Helm, LLM, ML, AI, Asyncio, Python, Pandas, HayStack, Azure Blob Storage, Azure DevOps, SQL Alchemy, Docker, Docker Compose, PySpark, PostgreSQL, FastAPI

Requirements

• 4+ years in backend/performance engineering (Python and/or C++) with production services.
• 1+ year hands-on with GPU-accelerated AI/ML inference (Triton/TensorRT/CUDA) in production.
• Proven delivery of NIM- or Triton-based microservices behind REST/gRPC (autoscaling, rollout strategies, monitoring).
• Practical experience profiling and removing GPU bottlenecks (memory, kernels, launch configs, batching, concurrency).
• Strong system design skills (throughput/latency/SLA) and high code quality (tests, reviews, docs).

Job responsibilities

• Design, build, and operate NIM-powered microservices (LLM, Embeddings, Reranker, ASR/TTS, VLM) for product features.
• Optimize inference end-to-end – TensorRT-LLM engines, quantization, batching, concurrency, KV-cache, CUDA kernels where needed.
• Package & deploy via Triton + Kubernetes (Helm), set up GPU scheduling, MIG/MPS, canary/blue-green strategies.
• Expose stable APIs (REST/gRPC), versioning, auth/rate-limits; deliver SDK/client wrappers for internal teams.
• Instrument – metrics/logs/traces (Prometheus/Grafana/Otel), DCGM, alerts, SLOs, runbooks, cost/capacity planning.
• Collaborate with DS/Platform/Product on priorities, model choices, and integration paths; ship incrementally.
• Maintain quality & security: tests, CI/CD, IaC, dependency hygiene, secrets management, network policies.
• Document designs, benchmarks, and operational playbooks.

Tools

• NVIDIA – NIM, Triton, TensorRT / TensorRT-LLM, CUDA, cuDNN, cuBLAS, NCCL, Nsight, DCGM
• Backend/AI – Python, C++, FastAPI, AsyncIO, PyTorch/ONNX, vector search/RAG
• Platform – Docker, Kubernetes, Terraform, Helm, Azure Blob/DevOps, PostgreSQL, Redis, Kafka, Grafana/Prometheus/Otel

Are you passionate about building impactful digital solutions and working with cutting-edge technologies? We are looking for a Junior Full Stack Developer to join our team and contribute to an exciting telecom infrastructure project.

CUSTOMER

Our customer is a leading Swedish telecommunications company, recognized for delivering innovative large-scale technology solutions across complex infrastructure environments. Sweden’s telecom sector is known for its advanced networks, high-speed connectivity, and pioneering role in 5G development. The company operates internationally, serving millions of users and partnering with global technology leaders to drive digital transformation.

PROJECT

The project involves developing a centralized portal that serves as a single source of truth for software components and their relationships with hardware systems. It ensures transparency in software-hardware dependencies and enables compatibility analysis across different component versions.

Key Technologies: Python (Django), AngularJS, Kubernetes, CI/CD, Jenkins

Job Description

• Contribute to technical solutions and write maintainable, high-quality code
• Develop new features and components, assist with refactoring, debugging, and software maintenance
• Participate in peer code reviews and follow established engineering practices
• Perform unit and integration testing to ensure software reliability
• Assist in analyzing requirements and preparing feature designs
• Create and maintain technical documentation
• Join conference calls and meetings with the Customer when required
• Be an active member of the SAFe Agile team, participating in estimation, grooming, and planning sessions

Qualifications

• 2+ years of experience working with Python
• Solid knowledge of JavaScript and TypeScript
• Experience with CI/CD pipelines and related tools
• Hands-on experience with Kubernetes
• Understanding of backend development principles and RESTful APIs
• Front-end development experience, including component-based architecture
• Knowledge of relational databases and data modeling concepts
• Familiarity with testing practices for both frontend and backend applications
• Basic understanding of cloud environments and deployment processes

• Strong Intermediate (B2) level of English or higher

   

WILL BE A PLUS:

• Experience with AngularJS

We are a dynamic iGaming company with over 5 years of experience and a team of 1,000+ specialists. Our portfolio includes 8 successful projects, loved by players and operating across Tier 1–3 markets.

At our core, we attract and value top talent, enabling us to streamline processes and confidently expand into new markets.

💼 Join us as an Email Marketing Manager and become part of a team that launches new projects, drives innovation, and shapes the future of iGaming! 🚀

🎯 Who we’re looking for?

A results-driven Email Marketing Specialist with hands-on experience in launching and optimizing email campaigns. You know how to segment, automate, A/B test, and analyze performance. Experience in iGaming or betting is a big plus. If you're detail-oriented, data-savvy, and creative — let’s talk

💼Your Responsibilities:

• Develop and launch email marketing campaigns targeting various user segments.
• Optimize campaign performance with a focus on improving open, click, and conversion rates.
• Localize email content and strategy according to regional market specifics.
• Analyze campaign results and prepare detailed performance reports.
• Conduct A/B testing of subject lines, content, and CTAs to enhance user engagement.
• Work across multiple communication channels including email and in-app/push notifications.
• Create and optimize email templates: promotional campaigns, trigger-based messages, automated flows, and newsletters.
• Manage and segment customer databases to ensure precise targeting.
• Collaborate with designers and copywriters to produce high-quality, engaging content aligned with the casino and sports betting verticals.
• Stay up-to-date with the latest trends and best practices in email marketing.
• Ensure all campaigns are compliant with data protection regulations and anti-spam laws.

📌What we’re looking for:

• Minimum 6 months of experience in email marketing (preferably within the online casino or sports betting industry).
• Proficiency in email marketing platforms such as Mailchimp, Customer.io, or similar ESPs.
• Experience in planning, executing, and optimizing email campaigns, including A/B testing.
• Solid understanding of segmentation strategies and trigger-based email flows.
• Basic knowledge of HTML and CSS for email template customization.
• Familiarity with analytics tools for campaign performance tracking and optimization.
• Strong attention to detail and excellent communication skills.
• Ability to collaborate effectively with cross-functional teams.

🎁 What we offer:

🌍 Remote work from anywhere in the world

💸 Competitive salary

🏖️ Paid vacation days

🤒 Paid sick leave

🚀 Career growth opportunities

💼 Professional and result-oriented environment