Jobs at Djinni

We are looking for a SAR Processing Engineer – AI with hands-on experience combining raw SAR signal processing and AI models for object and structure recognition. This role sits at the intersection of radar physics, signal processing, and machine learning. You will design AI models that work directly on raw radar returns, integrate them into deployable systems, and validate them through real-world testing.

Our client is building next-generation AI-powered SAR sensing systems for exploration, reconnaissance, and material-penetrating detection. We work with government and defense customers to develop systems that “see through everything.” You will join an elite engineering team working directly with the founders in a unique location—a former Berlin airport with massive outdoor testing areas.

Work Model

• On-site preferred: Remote, but 1 time per month, need to fly to Berlin for field tests.

Experience Requirements

• Mid-level: 3–4 years of professional experience in signal processing or ML, with at least 1+ year of hands-on experience specifically with Synthetic Aperture Radar (SAR).
• Senior level: 5+ years of professional experience in radar systems or advanced signal processing, with a proven track record of applying AI/ML to raw sensor data.
• Core Focus: This is not a pure ML role. We require a deep understanding of radar physics combined with AI expertise.

Key Responsibilities

• AI/ML Development: Design and implement robust models for processing raw SAR data (Level 0) for object detection, structure recognition, and automated classification.
• System Integration: Integrate AI models into deployable SAR payloads for airborne (UAV) platforms and build production-ready real-time processing frameworks.
• Performance Optimization: Optimize compute performance across CPU and GPU architectures (CUDA).
• Cross-functional Collaboration: Work closely with SAR system engineers, RF/Hardware teams, and software developers.
• Testing & Validation: Lead data collection and testing for AI model validation across the full lifecycle: from simulation to field deployment.

Required Qualifications

• SAR Expertise: Hands-on experience with Synthetic Aperture Radar and raw (Level 0) radar data.
• Programming: Strong skills in Python and/or C++.
• Technical Depth: Solid understanding of radar systems, RF fundamentals, signal processing, and SAR calibration/error correction.
• Acceleration: Experience with CUDA / GPU acceleration is a strong plus.
• Mindset: Ability to bridge the gap between algorithm R&D and deployable production-grade code.

Preferred Qualifications

• Experience with airborne SAR payloads (UAV, aircraft) or material-penetrating SAR (soil/foliage).
• Background in defense or government-funded projects.
• Experience with NATO-restricted or export-controlled technologies.

Why Join?

• Real Impact: Work on technology that goes from the lab directly to field deployment to solve real-world defense challenges.
• Ownership: Be an early engineer shaping both the product and the company’s technical roadmap.
• Incentives: Competitive compensation plus VSOP (shares) / equity packages.

Let’s start with what PLANEKS offers:

0. Fast and comfortable hiring process.

1. 100% remote work opportunity and flexitime - choose working hours between 8:00-20:00.

2. Manage your compensation $$$$ budget - Travel tickets, Work equipment, Health insurance, Software, Sport, Training.

3. Salary paid in USD + tax compensation. Revision every 12 months. We want everyone to be confident in what tomorrow brings.

4. Everything to provide a good rest. YES: Paid vacation, national holidays, sick leaves(and support in case of serious diseases). NO: overtime, work on weekends.

5. Regular feedback, mentorship, code review. Friendly and professional team that supports you. Well, we're proud of how we handle that. So you can always count on us.

6. Speaking clubs with a native speaker to constantly maintain your English level.

7. No bureaucracy - transparent processes and flat management. Working remotely means keeping things as simple as possible to work efficiently.

We propose something more significant than a job. PLANEKS means developing a new lifestyle for our colleagues and clients. So take your part in it!

Position Overview: We are looking for a highly motivated, detail-oriented, and adaptable Quality Control Engineer to join our dynamic team. The successful candidate will be responsible for ensuring the quality and reliability of our hospitality automation services. The Quality Control Engineer will play a critical role in establishing a structured testing process, ensuring the reliability and efficiency of our web application, and supporting the team’s development efforts.

The project:

Our client is transforming the hospitality industry with innovative solutions that optimize daily operations, enhance transparency, and drive profitability. 

Our flagship product automates tip management, and we’re expanding our suite of tools to streamline every aspect of hospitality operations.  

Required Hard Skills:

• Strong experience in software quality assurance, test planning, and execution.
• Extensive experience in manual testing of web applications, including user interface testing across desktop, tablet, and mobile devices.
• Proficiency in executing functional, regression, and integration tests to ensure the application’s stability and reliability.
• Ability to design and execute detailed test cases based on business requirements and user stories.
• Expertise in testing APIs and integrations with multiple third-party systems, ensuring seamless data flow and functionality.
• Hands-on experience testing payment gateways, processing flows, and payroll systems, ensuring accuracy, security, and compliance.
• Ability to test and validate complex algorithms and data-driven calculations, ensuring accuracy and reliability.
• Strong skills in using defect tracking tools like Jira or Trello for logging, tracking, and managing bugs.

Nice to Have:

• Basic understanding of Python and JavaScript (React) to support the development of test scripts and understanding of the application’s codebase.
• Experience with version control systems like Git for managing test scripts and collaborating with the development team.
• Exposure to continuous integration and deployment processes to support testing within the development pipeline.
• Familiarity with automation testing tools such as Selenium or Cypress, with a willingness to learn and implement automation testing gradually.
• Knowledge of performance and security testing.

Soft Skills: 

• Adaptability. Ability to thrive in a fast-paced, constantly changing environment, quickly adapting to new requirements and challenges.
• Collaboration. Strong team player who can effectively engage with developers, project managers, and other stakeholders.
• Communication. Excellent verbal and written communication skills to convey testing results, issues, and recommendations clearly.
• Problem-Solving. Strong analytical skills to identify issues and propose effective solutions.
• Initiative. Proactive in identifying areas for improvement and driving change to enhance product quality and team efficiency.

Key Responsibilities:

• Quickly gain an in-depth understanding of the project to contribute effectively and efficiently, ensuring a smooth testing process.
• Establishing a structured and efficient testing cycle that improves product quality without slowing down development.
• Develop comprehensive test plans and test cases based on product requirements and user scenarios to ensure all features are tested thoroughly.
• Conduct thorough manual testing of the web application, focusing on functionality, usability, and integration with third-party systems. 
• Conduct thorough testing of complex calculation algorithms to ensure accuracy and reliability in various tipping models.
• Identify, document, and report bugs and issues clearly and accurately, working closely with the development team to resolve them.
• Work closely with developers, project managers, and stakeholders to understand the product and its requirements, identify, document, and resolve bugs and issues.

Let’s start with what PLANEKS offers:

0. Fast and comfortable hiring process.

1. 100% remote work opportunity and flexitime - choose working hours between 8:00-20:00 (Ability to work closely to EST time zone will be a big advantage).

2. Manage your compensation $$$$ budget - Travel tickets, Work equipment, Health insurance, Software, Sport, Training.

3. Salary paid in USD + tax compensation. Revision every 12 months. We want everyone to be confident in what tomorrow brings.

4. Everything to provide a good rest. YES: Paid vacation, national holidays, sick leaves(and support in case of serious diseases). NO: overtime, work on weekends.

5. Regular feedback, mentorship, code review. Friendly and professional team that supports you. Well, we're proud of how we handle that. So you can always count on us.

6. Speaking clubs with a native speaker to constantly maintain your English level.

7. No bureaucracy - transparent processes and flat management. Working remotely means keeping things as simple as possible to work efficiently.

We propose something more significant than a job. PLANEKS means developing a new lifestyle for our colleagues and clients. So take your part in it!

Requirements:

• 5+ years building production web applications with React and TypeScript.
• Strong product/UI sensibility - cares about spacing, visual hierarchy, typography, and interaction details.
• Experience with Next.js.
• Experience with advanced CSS.
• Comfortable building real interaction patterns: transitions, loading states, empty states, error states, skeleton screens.
• Can take a Figma comp and build it accurately, filling in gaps (missing states, responsive breakpoints) with good judgment rather than waiting for design to specify every pixel.
• Performance awareness - understands bundle size, rendering costs, lazy loading, when to optimize.
• MUI (Material UI) - theming, component composition, customization.
• TanStack Query or similar async state management.
• Formik or equivalent form library.
• Docker fundamentals and container-based workflows.
• CI/CD pipelines (GitHub Actions).

Responsibilities:

Day-to-day: Build and ship front-end features in React/Next.js/TypeScript. Translate Figma designs into polished, production-ready UI. Care about the visual details.

Ongoing: Build reusable components that become the team's shared vocabulary. Write front-end code that's clean enough to be the example others follow. Identify UI inconsistencies and fix them without being asked. Push work to a high standard before it reaches QA.

Over time: Establish front-end patterns and conventions that make the whole team's UI work more consistent. Contribute to a component library that accelerates future development. Help other devs level up their front-end skills through code reviews and well-structured code.

Nice to Have:

• Accessibility awareness - knows ARIA patterns, keyboard navigation, screen reader basics.
• Animation proficiency - understands easing, timing, and restraint.
• Backend comfort (Python/Django) - can read and modify backend code when needed, not just consume APIs.
• Experience with data-heavy SaaS: tables, filters, dashboards, complex statuses, collapsing dense data into good mobile UX.
• Experience building or contributing to a component library or design system.
• Ability to have a significant overlap with EST hours.

We are looking for a junior backend VLSI engineer to join our Physical Design team.

This role is ideal for new graduates with strong academic foundations in digital design and VLSI who want to learn and execute a full RTL→GDSII implementation flow using Synopsys tools.

You will gain hands-on experience working on advanced semiconductor technologies, including nodes down to 7 nm, 5 nm, 3 nm, and 2 nm.

Responsibilities:

Assist in synthesis (Design Compiler / Fusion Compiler) from RTL to gate-level netlist

Support floorplanning, power planning, and clock tree design

Perform place and route (P&R) using ICC2 / Fusion Compiler

Contribute to timing analysis and closure using PrimeTime (STA)

Run physical verification checks: DRC, LVS, antenna, IR-drop, EM

Prepare and validate design constraints (SDC, clock definitions, I/O timing)

Help generate and validate physical deliverables (LEF/DEF, SPEF, SDF)

Collaborate with RTL, DFT, package, verification, and integration teams

Document design steps, results, and signoff data

Required Qualifications:

B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or related field

Strong understanding of digital logic, synchronous design, and timing fundamentals

Academic exposure to VLSI backend flows

Basic familiarity with: synthesis, place & route, STA

Scripting skills (TCL, Python, Shell)

Strong analytical and problem-solving mindset

Motivation to learn deep-submicron implementation techniques (FinFET and GAA nodes)

Nice-to-Have Skills

Exposure to Synopsys tools (DC, ICC2, PT) through coursework or projects

Understanding of setup/hold timing, OCV, derates, clock uncertainty

Basic knowledge of physical effects: congestion, crosstalk, IR-drop, EM

Linux environment experience

Familiarity with Git or similar tools

What We Offer:

Hands-on work on advanced semiconductor nodes down to 2 nm

Full training in modern RTL→GDSII physical design flows

Mentorship from senior PD and STA engineers

Opportunity to work on high-performance ASICs and SoC designs

Clear growth path toward P&R specialist, STA engineer, PD lead, or chip integration engineer

About the Role:

We are seeking a motivated Junior Package Engineer with PCB design experience to join our IC packaging and signal/power integrity team.

You will support the development of advanced semiconductor packages and perform SI/PI analysis for high-speed interfaces such as Ethernet, PCIe, DDR, and SerDes.

Responsibilities:

• Assist in IC package design (substrate layout, stack-up, routing, DRC checks)
• Support package floorplanning and die/ball map development
• Work with senior engineers to run SI simulations (S-parameters, insertion loss, eye diagrams)
• Perform PI/PDN analysis (IR drop, decap planning, impedance profiles)
• Translate PCB experience into package-level routing constraints (differential pair rules, impedance control)
• Help model high-speed interfaces: Ethernet, PCIe, DDR, SerDes
• Collaborate with silicon, system, and PCB teams on end-to-end interconnect design
• Document design guidelines, simulation results, and engineering reports

Required Qualifications:

• Experience with PCB design tools (Altium, OrCAD, Allegro, KiCad, or similar)
• Understanding of high-speed differential routing and board-level signal integrity basics
• Familiarity with impedance control, vias, stackups, return paths, PDN concepts
• Exposure to interfaces such as Ethernet, PCIe, DDR
• Basic scripting or automation skills (Python/Matlab preferred)
• Strong problem-solving abilities and attention to detail
• High motivation to learn package design and SI/PI methodologies
• Nice-to-Have Skills
• Familiarity with package design tools: Cadence SIP/APD, Xpeedic, Mentor Xpedition
• Exposure to SI/PI simulation tools: ANSYS SIwave, HFSS, Sigrity, ADS
• Understanding of flip-chip, BGA, RDL, 2.5D/3D packaging

• Knowledge of SerDes, USB, LPDDR, or high-speed PHY design principles

   

What We Offer: 

• Full training in IC packaging, SI/PI analysis, and advanced interconnect design
• Opportunity to work with cutting-edge technologies (PCIe Gen5/6, DDR5/6, chiplets)
• Mentorship from senior package, SI, and system engineers
• A clear growth path toward package architect, SI/PI lead, or chiplet interconnect specialist

About the Role:

We are seeking a motivated Junior Verification Engineer to join our VLSI design and verification team.

This is an excellent opportunity for new graduates with strong academic training in digital design, verification methodologies, and SystemVerilog/UVM.

Responsibilities:

Develop and execute verification testbenches using Verilog/SystemVerilog and UVM

Implement functional and constrained-random tests for block-level and SoC-level designs

Create coverage models (functional, code, assertion-based) and drive coverage closure

Debug simulation failures, interface mismatches, and RTL issues

Write and maintain scoreboards, monitors, agents, drivers, and checkers in UVM

Review design specifications, extract test requirements, and build verification plans

Run regressions, triage failures, and document results

Collaborate closely with RTL designers, DFT, backend, and system architects

Required Qualifications:

B.Sc. or M.Sc. in Electrical/Computer Engineering or related field

Strong academic background in digital logic, computer architecture, and VLSI design

Hands-on experience with Verilog and SystemVerilog (labs, projects, internship)

Basic understanding of UVM methodology

Familiarity with simulation tools (VCS, QuestaSim, Xcelium or similar)

Ability to read and understand RTL code

Good analytical and debugging skills

Strong motivation to grow in advanced functional verification

Nice-to-Have Skills:

Coursework or project experience with UVM testbench development

Familiarity with assertion-based verification (SVA)

Basic scripting (Python, Perl, Shell, TCL)

Experience with coverage-driven verification

Exposure to SoC-level interfaces (AXI, PCIe, DDR, Ethernet, SPI, I2C)

What We Offer:

Full training in modern verification methodologies (UVM, SVA, CRV)

Work with cutting-edge IPs and SoC architectures

Mentorship from senior verification and architecture teams

Clear growth path toward UVM specialist, verification lead, or architect

We are looking for highly motivated junior engineers to join our Design-for-Test (DFT) team.

This is an excellent opportunity for graduates who want to build expertise in Scan, Memory BIST, and JTAG within advanced VLSI development.

Responsibilities:

Learn and support implementation of scan insertion and scan chain architecture

Assist in ATPG pattern generation and test coverage analysis

Participate in Memory BIST (MBIST) integration and verification

Work with JTAG / IEEE 1149.1 boundary scan concepts and flows

Help debug test-related issues at RTL and gate level

Collaborate with senior DFT engineers on SoC-level test strategy

Required Background:

Academic knowledge in digital logic, VLSI design, and computer architecture

Basic familiarity with DFT concepts: scan, ATPG, BIST, boundary scan

Understanding of Verilog or VHDL

Scripting basics (Python, TCL, Shell)

Good analytical and problem-solving skills

Strong motivation to learn industry-standard DFT tools and flows

What We Offer:

Full training in Scan, MBIST, JTAG, ATPG, and DFT methodologies

Mentorship by experienced DFT engineers

Exposure to advanced SoC development flows and signoff

Growth path toward senior DFT, test architecture, or silicon bring-up roles

About the Role:

We are seeking a motivated Junior Package Engineer with PCB design experience to join our IC packaging and signal/power integrity team.

You will support the development of advanced semiconductor packages and perform SI/PI analysis for high-speed interfaces such as Ethernet, PCIe, DDR, and SerDes.

Responsibilities:

• Assist in IC package design (substrate layout, stack-up, routing, DRC checks)
• Support package floorplanning and die/ball map development
• Work with senior engineers to run SI simulations (S-parameters, insertion loss, eye diagrams)
• Perform PI/PDN analysis (IR drop, decap planning, impedance profiles)
• Translate PCB experience into package-level routing constraints (differential pair rules, impedance control)
• Help model high-speed interfaces: Ethernet, PCIe, DDR, SerDes
• Collaborate with silicon, system, and PCB teams on end-to-end interconnect design
• Document design guidelines, simulation results, and engineering reports

Required Qualifications:

• Experience with PCB design tools (Altium, OrCAD, Allegro, KiCad, or similar)
• Understanding of high-speed differential routing and board-level signal integrity basics
• Familiarity with impedance control, vias, stackups, return paths, PDN concepts
• Exposure to interfaces such as Ethernet, PCIe, DDR
• Basic scripting or automation skills (Python/Matlab preferred)
• Strong problem-solving abilities and attention to detail

• High motivation to learn package design and SI/PI methodologies

   

  Nice-to-Have Skills

• Familiarity with package design tools: Cadence SIP/APD, Xpeedic, Mentor Xpedition
• Exposure to SI/PI simulation tools: ANSYS SIwave, HFSS, Sigrity, ADS
• Understanding of flip-chip, BGA, RDL, 2.5D/3D packaging

• Knowledge of SerDes, USB, LPDDR, or high-speed PHY design principles

   

What We Offer: 

• Full training in IC packaging, SI/PI analysis, and advanced interconnect design
• Opportunity to work with cutting-edge technologies (PCIe Gen5/6, DDR5/6, chiplets)
• Mentorship from senior package, SI, and system engineers
• A clear growth path toward package architect, SI/PI lead, or chiplet interconnect specialist

About the Role:

We are seeking a motivated Junior Package Engineer with PCB design experience to join our IC packaging and signal/power integrity team.

You will support the development of advanced semiconductor packages and perform SI/PI analysis for high-speed interfaces such as Ethernet, PCIe, DDR, and SerDes.

Responsibilities:

• Assist in IC package design (substrate layout, stack-up, routing, DRC checks)
• Support package floorplanning and die/ball map development
• Work with senior engineers to run SI simulations (S-parameters, insertion loss, eye diagrams)
• Perform PI/PDN analysis (IR drop, decap planning, impedance profiles)
• Translate PCB experience into package-level routing constraints (differential pair rules, impedance control)
• Help model high-speed interfaces: Ethernet, PCIe, DDR, SerDes
• Collaborate with silicon, system, and PCB teams on end-to-end interconnect design
• Document design guidelines, simulation results, and engineering reports

Required Qualifications:

• Experience with PCB design tools (Altium, OrCAD, Allegro, KiCad, or similar)
• Understanding of high-speed differential routing and board-level signal integrity basics
• Familiarity with impedance control, vias, stackups, return paths, PDN concepts
• Exposure to interfaces such as Ethernet, PCIe, DDR
• Basic scripting or automation skills (Python/Matlab preferred)
• Strong problem-solving abilities and attention to detail

• High motivation to learn package design and SI/PI methodologies

   

  Nice-to-Have Skills

• Familiarity with package design tools: Cadence SIP/APD, Xpeedic, Mentor Xpedition
• Exposure to SI/PI simulation tools: ANSYS SIwave, HFSS, Sigrity, ADS
• Understanding of flip-chip, BGA, RDL, 2.5D/3D packaging

• Knowledge of SerDes, USB, LPDDR, or high-speed PHY design principles

   

What We Offer: 

• Full training in IC packaging, SI/PI analysis, and advanced interconnect design
• Opportunity to work with cutting-edge technologies (PCIe Gen5/6, DDR5/6, chiplets)
• Mentorship from senior package, SI, and system engineers
• A clear growth path toward package architect, SI/PI lead, or chiplet interconnect specialist

We design integrated circuits for consumer, medical and automotive markets. The majority of these designs are complex SoC/ASIC architectures that integrate IPs, such as ARM and RISC-V CPUs and peripherals, DSP cores, analog cells and other IPs with progressive technology nodes: 24, 10, 7,  3 nanometers.

In our daily work we constantly face challenges that requires out of box thinking. This makes our lives an interesting and challenging adventure. Such attitude permits creation of products full of features that often outperform market. We are constant learners, the same we expect from our new employees. Hence, we’d be happy to meet passionate and keen on learning, bright young individuals.

Below is a brief list of skills/knowledge that ideally suit our job profile. Still it’s not an issue if you don’t possess some of those. To our opinion the fundamental engineer’s skills are problem solving and ability to learn.

Desired knowledge you may possess:

• Good understanding of digital/analog electronics and semiconductors physics
• FPGA placement and routing using EDA tools
• Experience with PCB design using such tools such as OrCAD, Altium Designer or similar
• Basic knowledge of scripting languages such as Tcl, Python, Make
• Beginner’s level of English

Optional skills you may have:

• FPGA design using HDLs or schematics editor
• Embedded systems design using IDEs such as Keil, AtmelStudio, IAR

We offer:

• Part- or full-time employment, flexible schedule
• On-job training in our Kyiv office with high skilled professionals
• Potential growth in the direction of ASIC design
• Paid sick leave and vacation

We design integrated circuits for consumer, medical and automotive markets. The majority of these designs are complex SoC/ASIC architectures that integrate IPs, such as ARM and RISC-V CPUs and peripherals, DSP cores, analog cells and other IPs with progressive technology nodes: 14, 10, 8, 7 nanometers.

You will be responsible for digital logic design and verification. Besides, you'd be able to learn and improve related methodologies. Below is a brief list of skills/knowledge that ideally suit our job profile. Still it’s not an issue if you don’t possess some of those. To our opinion the fundamental engineer’s skills are analytical thinking and ability to learn.

Essential qualifications:

-Degree in Electronics or related fields

-Good understanding of digital electronics

-Experience with EDA tools (Xilinx, Mentor Graphics, Synopsys or similar)

-Beginner’s level of English or higher

Optional qualifications you may have:

-FPGA design using HDL (Verilog, VHDL) or schematics editor

-IC design verification using System Verilog

-CPU architecture knowledge, embedded SW development

We offer:

-Full-time employment, flexible schedule

-On-job training in our Kyiv office with high skilled professionals

-Potential growth in directions of ASIC/FPGA design

-Social benefits, modern and comfortable office facilities

N-iX is a global software development company founded in 2002, connecting over 2,400+ tech professionals across 40+ countries. We deliver innovative technology solutions in cloud computing, data analytics, AI, embedded software,IoT, and more to global industry leaders and Fortune 500 companies. Join us to create technology that drives real change for businesses and people across the world.

About the position

We are seeking a Lead Observability Engineer with proven expertise in designing, operating, and scaling analytical data systems, specifically ClickHouse or similar distributed databases. In this role, you will take a hands-on leadership position in architecting and migrating our existing custom Cosmos telemetry system storage to a robust, high-performing ClickHouse-based solution. You’ll be instrumental in building the foundation for alerting, notification, and telemetry workflows that empower visibility into our production systems.

Responsibilities

• Lead the migration of DocuSign’s custom Cosmos telemetry storage solution to a scalable ClickHouse end-to-end platform
  Architect, deploy, and productionize ClickHouse clusters for high-volume observability, alerting, notifications, and telemetry workloads
• Own the operations and reliability of ClickHouse environments (self-managed or cloud), including upgrades, scaling, backup/recovery, and incident response
• Tune performance, query optimization, and storage strategies (replication, sharding, compactions/merges)
• Develop robust alerting and monitoring frameworks for the ClickHouse platform and related infrastructure
• Collaborate with developers and SREs to define requirements and best practices around telemetry, data pipelines, and observability tooling
• Drive automation of platform management leveraging Kubernetes at scale

Requirements

• Strong hands-on experience hosting and operating ClickHouse (self-managed or cloud), or a similar distributed analytical database, in production environments
• In-depth understanding of distributed data systems internals, including storage engines, replication, sharding, compactions/merges, and query optimization
• Proven experience designing, deploying, and scaling ClickHouse for observability or high-volume telemetry use cases
• Production experience running analytics infrastructure on Kubernetes at scale
• Expertise in troubleshooting, performance analysis, and reliability engineering for large-scale database systems

Would be a plus

• Experience with observability stacks (Prometheus, Grafana, OpenTelemetry, etc.)
• Development experience with infrastructure-as-code and automation tools (Terraform, Helm, etc.)
• Knowledge of cloud-native observability solutions and best practices

We offer*:

• Flexible working format - remote, office-based or flexible
• A competitive salary and good compensation package
• Personalized career growth
• Professional development tools (mentorship program, tech talks and trainings, centers of excellence, and more)
• Active tech communities with regular knowledge sharing
• Education reimbursement
• Memorable anniversary presents
• Corporate events and team buildings
• Other location-specific benefits

*not applicable for freelancers

We design integrated circuits for consumer, medical and automotive markets. The majority of these designs are complex SoC/ASIC architectures that integrate IPs, such as ARM and RISC-V CPUs and peripherals, DSP cores, analog cells and other IPs with progressive technology nodes: 24, 10, 7,  3 nanometers.

In our daily work we constantly face challenges that requires out of box thinking. This makes our lives an interesting and challenging adventure. Such attitude permits creation of products full of features that often outperform market. We are constant learners, the same we expect from our new employees. Hence, we’d be happy to meet passionate and keen on learning, bright young individuals.

Below is a brief list of skills/knowledge that ideally suit our job profile. Still it’s not an issue if you don’t possess some of those. To our opinion the fundamental engineer’s skills are problem solving and ability to learn.

Desired knowledge you may possess:

• Good understanding of digital/analog electronics and semiconductors physics
• FPGA placement and routing using EDA tools
• Experience with PCB design using such tools such as OrCAD, Altium Designer or similar
• Basic knowledge of scripting languages such as Tcl, Python, Make
• Beginner’s level of English

Optional skills you may have:

• FPGA design using HDLs or schematics editor
• Embedded systems design using IDEs such as Keil, AtmelStudio, IAR

We offer:

• Part- or full-time employment, flexible schedule
• On-job training in our Kyiv office with high skilled professionals
• Potential growth in the direction of ASIC design
• Paid sick leave and vacation

N-iX is a global software development company founded in 2002, connecting over 2,400+ tech professionals across 40+ countries. We deliver innovative technology solutions in cloud computing, data analytics, AI, embedded software,IoT, and more to global industry leaders and Fortune 500 companies. Join us to create technology that drives real change for businesses and people across the world.

Our client is a global UK-based financial services and investment banking organization developing an AI-powered document processing and automation platform used across multiple businesses within the wider banking group. The platform leverages modern cloud and AI technologies to transform legacy workflows, enhance data quality, and accelerate digital decision-making.

Position Overview:
 

We are looking for a Tech Lead Full Stack Engineer with strong hands-on engineering expertise leading agile software development teams. The ideal candidate will define and drive the technical strategy of the platform, guide engineers in delivering scalable and secure systems, and actively contribute to architectural decisions and solution design.

This role requires both strong technical depth and leadership capabilities, particularly in environments involving Google Cloud, microservices, APIs, Python and data-intensive processing.

The Tech Lead will work closely with product, architecture, data science, and engineering teams to ensure high-quality delivery and alignment with business outcomes.

Join Our Team & Earn Exciting Bonuses!
As a special incentive, we’re offering a Welcome Bonus of $3,000 USD for a new hire. Plus, if you refer a friend who gets hired, you’ll receive a Referral Bonus of $2000 USD!

Key Responsibilities:

• Define and communicate the technical vision, architecture, and engineering roadmap for the team and platform.
• Lead engineers, conduct code reviews, provide architectural guidance, and ensure adherence to engineering standards.
• Lead the technical delivery lifecycle from design and development to deployment and maintenance.
• Build scalable, high-performance microservices and UI and APIs using modern frameworks and cloud-native design principles.
• Oversee integration of AI components (E.g Google Cloud, Vertex AI, Gemini models, and LLM evaluation frameworks)
• Promote test-driven development, automate testing pipelines, and ensure robust, maintainable code.
• Work with product managers, architects, BAs, and business teams to translate business needs into technical solutions.
• Contribute to product strategy, identify technical opportunities, and propose improvements to shape future releases.
• Drive best practices for cloud infrastructure, security, observability, and performance optimization on Google Cloud.
   

Requirements:

• 8+ years of experience in software engineering with at least 3+ years in a Tech/Team Lead role.
• Strong background in software/platform/database design in data-heavy or distributed environments.
• Hands-on experience with microservices, React JS, and cloud-native architectures.
• Proficiency in Python.
• Solid Cloud experience (GCP is prefferable) 
• Hands-on experience building and integrating LLM pipelines, handling conversation memory, and long-running workflows
• Proficiency in RAG architectures with a focus on optimized search retrieval and scalable data indexing strategies
• Practical experience with AI output validation, automated evaluation strategies, and secure AI integration
• Experience with LLM observability, tracing (e.g., LangSmith, Langfuse), and token usage/cost optimization
• Experience implementing automated testing frameworks, CI/CD pipelines, and TDD/BDD practices.
• Strong understanding of software engineering principles: scalability, performance, reliability, observability.
• Proven experience leading engineering teams in agile delivery environments.
• Advanced English and excellent communication skills and ability to work with both technical and non-technical stakeholders.
   

Nice to Have:

• Prior exposure to document processing platforms, OCR, NLP, or workflow automation.
• Experience in financial services or other regulated industries.
• Familiarity with architectural frameworks (C4 modeling, DDD, event-driven systems).

We offer*:

• Flexible working format - remote, office-based or flexible
• A competitive salary and good compensation package
• Personalized career growth
• Professional development tools (mentorship program, tech talks and trainings, centers of excellence, and more)
• Active tech communities with regular knowledge sharing
• Education reimbursement
• Memorable anniversary presents
• Corporate events and team buildings
• Other location-specific benefits

*not applicable for freelancers

N-iX is a global software development company founded in 2002, connecting over 2,400+ tech professionals across 40+ countries. We deliver innovative technology solutions in cloud computing, data analytics, AI, embedded software,IoT, and more to global industry leaders and Fortune 500 companies. Join us to create technology that drives real change for businesses and people across the world.

Our client is a global UK-based financial services and investment banking organization developing an AI-powered document processing and automation platform used across multiple businesses within the wider banking group. The platform leverages modern cloud and AI technologies to transform legacy workflows, enhance data quality, and accelerate digital decision-making.

Position Overview:
 

We are looking for a Tech Lead Full Stack Engineer with strong hands-on engineering expertise leading agile software development teams. The ideal candidate will define and drive the technical strategy of the platform, guide engineers in delivering scalable and secure systems, and actively contribute to architectural decisions and solution design.

This role requires both strong technical depth and leadership capabilities, particularly in environments involving Google Cloud, microservices, APIs, Python and data-intensive processing.

The Tech Lead will work closely with product, architecture, data science, and engineering teams to ensure high-quality delivery and alignment with business outcomes.

Join Our Team & Earn Exciting Bonuses!
As a special incentive, we’re offering a Welcome Bonus of $3,000 USD for a new hire. Plus, if you refer a friend who gets hired, you’ll receive a Referral Bonus of $2000 USD!

Key Responsibilities:

• Define and communicate the technical vision, architecture, and engineering roadmap for the team and platform.
• Lead engineers, conduct code reviews, provide architectural guidance, and ensure adherence to engineering standards.
• Lead the technical delivery lifecycle from design and development to deployment and maintenance.
• Build scalable, high-performance microservices and UI and APIs using modern frameworks and cloud-native design principles.
• Oversee integration of AI components (E.g Google Cloud, Vertex AI, Gemini models, and LLM evaluation frameworks)
• Promote test-driven development, automate testing pipelines, and ensure robust, maintainable code.
• Work with product managers, architects, BAs, and business teams to translate business needs into technical solutions.
• Contribute to product strategy, identify technical opportunities, and propose improvements to shape future releases.
• Drive best practices for cloud infrastructure, security, observability, and performance optimization on Google Cloud.
   

Requirements:

• 8+ years of experience in software engineering with at least 3+ years in a Tech/Team Lead role.
• Strong background in software/platform/database design in data-heavy or distributed environments.
• Hands-on experience with microservices, React JS, and cloud-native architectures.
• Proficiency in Python.
• Solid Cloud experience (GCP is prefferable) 
• Hands-on experience building and integrating LLM pipelines, handling conversation memory, and long-running workflows
• Proficiency in RAG architectures with a focus on optimized search retrieval and scalable data indexing strategies
• Practical experience with AI output validation, automated evaluation strategies, and secure AI integration
• Experience with LLM observability, tracing (e.g., LangSmith, Langfuse), and token usage/cost optimization
• Experience implementing automated testing frameworks, CI/CD pipelines, and TDD/BDD practices.
• Strong understanding of software engineering principles: scalability, performance, reliability, observability.
• Proven experience leading engineering teams in agile delivery environments.
• Advanced English and excellent communication skills and ability to work with both technical and non-technical stakeholders.
   

Nice to Have:

• Prior exposure to document processing platforms, OCR, NLP, or workflow automation.
• Experience in financial services or other regulated industries.
• Familiarity with architectural frameworks (C4 modeling, DDD, event-driven systems).

We offer*:

• Flexible working format - remote, office-based or flexible
• A competitive salary and good compensation package
• Personalized career growth
• Professional development tools (mentorship program, tech talks and trainings, centers of excellence, and more)
• Active tech communities with regular knowledge sharing
• Education reimbursement
• Memorable anniversary presents
• Corporate events and team buildings
• Other location-specific benefits

*not applicable for freelancers