SoC Verification Engineer

Join Innoneers – Shaping the Future of Software Engineering!
 

At Innoneers, we don’t just build software; we engineer innovation. We are a dynamic software development company dedicated to transforming complex business challenges into seamless digital experiences. Specializing in Web, Mobile, and Cloud solutions, we pride ourselves on our technical agility and "Engineering Excellence" mindset.
 

As we scale our operations, we are looking for a passionate SoC Verification Engineer to join our team. If you thrive in an environment where clean code meets cutting-edge technology (Node.js, React, AWS, Python) and want to make a tangible impact on global projects in E-commerce, Fintech, and Logistics, Innoneers is the place for you.

We will trust you with:

• Develop and maintain SystemVerilog/UVM-based verification environments at both module and SoC level;
• Write test sequences, define functional coverage models, and ensure coverage closure;
• Debug simulation results using waveform tools and collaborate with design teams to resolve issues;
• Drive constrained-random stimulus generation and continuous improvements in our verification methodology;
• Apply modern EDA tools and automate verification flows to maximize speed and quality;
• Contribute to quality assurance, release-readiness, and design-test alignment for every chip.
   

What you’ll need to succeed:

• 8+ years of digital verification, including 4+ years of constrained-random verification with UVM.
• 2+ years of embedded C development for SoC verification.
• Experience designing verification architecture from design specifications and creating test plans.
• Ability to translate functional requirements into functional coverage models.
• Skilled in constrained-random stimulus generation and coverage analysis/closure.
• Strong expertise in root-cause analysis and debugging SystemVerilog RTL.
• Proficiency in scripting with Python or similar languages.
• Solid experience with Linux, bash, or equivalent environments.
• Proficient with commercial EDA tools.
• Experience collaborating effectively with cross-functional teams.
• Hands-on experience with UVM verification architecture and vertical reuse of lower-level UVCs/environments.
• Skilled in mixed-language simulation and system modeling.
• Experience with effort estimation, project planning, scheduling, and tracking.

• Proven ability to lead and mentor a small team.

   

Nice-to-haves:

• Experience with SystemC for modeling and simulation.
• Knowledge of UPF and low-power verification methodologies.
• Exposure to formal verification techniques.
• Hands-on experience with FPGA validation and bring-up.
• Experience with full-chip emulation and bring-up.
• Familiarity with OpenOCD/GDB for software-driven verification.
• Experience in SystemVerilog RTL design.

If you're ready to shape the future of technology with us, apply and let's talk!