Junior Package / SI/PI Engineer (Entry Level)

About the Role:

We are seeking a motivated Junior Package Engineer with PCB design experience to join our IC packaging and signal/power integrity team.

You will support the development of advanced semiconductor packages and perform SI/PI analysis for high-speed interfaces such as Ethernet, PCIe, DDR, and SerDes.

Responsibilities:

• Assist in IC package design (substrate layout, stack-up, routing, DRC checks)
• Support package floorplanning and die/ball map development
• Work with senior engineers to run SI simulations (S-parameters, insertion loss, eye diagrams)
• Perform PI/PDN analysis (IR drop, decap planning, impedance profiles)
• Translate PCB experience into package-level routing constraints (differential pair rules, impedance control)
• Help model high-speed interfaces: Ethernet, PCIe, DDR, SerDes
• Collaborate with silicon, system, and PCB teams on end-to-end interconnect design
• Document design guidelines, simulation results, and engineering reports

Required Qualifications:

• Experience with PCB design tools (Altium, OrCAD, Allegro, KiCad, or similar)
• Understanding of high-speed differential routing and board-level signal integrity basics
• Familiarity with impedance control, vias, stackups, return paths, PDN concepts
• Exposure to interfaces such as Ethernet, PCIe, DDR
• Basic scripting or automation skills (Python/Matlab preferred)
• Strong problem-solving abilities and attention to detail
• High motivation to learn package design and SI/PI methodologies
• Nice-to-Have Skills
• Familiarity with package design tools: Cadence SIP/APD, Xpeedic, Mentor Xpedition
• Exposure to SI/PI simulation tools: ANSYS SIwave, HFSS, Sigrity, ADS
• Understanding of flip-chip, BGA, RDL, 2.5D/3D packaging

• Knowledge of SerDes, USB, LPDDR, or high-speed PHY design principles

   

What We Offer: 

• Full training in IC packaging, SI/PI analysis, and advanced interconnect design
• Opportunity to work with cutting-edge technologies (PCIe Gen5/6, DDR5/6, chiplets)
• Mentorship from senior package, SI, and system engineers
• A clear growth path toward package architect, SI/PI lead, or chiplet interconnect specialist