FPGA Design Engineer

The expected Skills And Experience:

• 5+ year experience in FPGA or VLSI (FrontEnd) design; 
• Strong Verilog/SystemVerilog skills (SystemVerilog is preferable); 
• C/C++ at intermediate level; 
• Implementing Lint Clean RTL based on C/C++ description; 
• Experience with SDC constraints and STA analysis; 
• Understanding CDC, RDC and Low Power design practises; 
• Understanding Verification methodologies (UVM); 
• Fixed Point DSP algorithms implementation experience; 

What you will do:

• Responsible for a module Lint clean RTL implementation based on the requirements. 
• Responsible for integrating third party IP into design. 
• Be able to add sequence/tests to the existing UVM environment. 
• Analyze code coverage and fix the holes if any. 
• Create SDC constraints for the modules you are responsible for. 
• Fix module related timing violation. 
• Deploy stable module implementation for system integration.