System Verilog (UVM) Engineer / Verilog Design Engineer

Samsung R&D Institute Ukraine is looking for an System Verilog verification and Verilog Design Engineer to join our team.

We are looking for an engineer to take part in Verilog-based HW IP Core development and UVM-based verification targeted for Samsung consume electronics in use by hundreds of millions of users worldwide. We promise cutting-edge technologies, decision-making participation, smart team and cookies.

More specifically you will:
 

- Design, develop and test RTL (Verilog, System Verilog) code for HW IP Cores

- Participate in research activities and strategic prototyping for future Samsung products

Qualifications and Skills:
 

- 5 years of hands-on experience with System Verilog (UVM) test bench development experience

- 5 years of hands-on experience with Verilog RTL development experience

- At least hands-on experience with C language

- Understanding principles of object-oriented programming

- At least Bachelor degree in Electronics or related field

Will be a plus:
 

- Pseudo-random, functional coverage verification methodologies, UVM

- SystemVerilog

- FPGA platform development and testing

- Proficiency in a Shell scripting (Python basic level)

- Experience with Linux environments

- Mathematical and algorithmic background

- Good technical English

Working Conditions:

- official employment - GIG contract

- remote work is possible as well as work in Kyiv office

Benefits:

- competitive salary, annual salary review, annual bonuses

- paid 28 work days of annual vacations and sick leaves

- opportunity to become an inventor of international patents with paid bonuses

- medical & life insurance for employees and their children

- paid lunches

- discounts to Samsung products, services

- regular education and self-development on internal courses and seminars

- hybrid work format, working in office is required for some tasks