Jobs ASIC / Chip Design

A unique opportunity to take part in building an R&D team for a global company.

We are seeking highly experienced and visionary formal verification engineers to contribute to the development of advanced AI connectivity architectures and help define the formal verification methodology from the ground up.

Responsibilities:

• Define and execute formal verification strategies and methodologies for complex SoCs, IPs, and networking architectures (Switches, NICs, SmartNICs).
• Develop, implement, and maintain formal verification environments and test plans from concept to production.
• Specify formal properties, assertions, and constraints using formal tools and SystemVerilog Assertions (SVA).
• Own the formal verification environment, including setup, maintenance, and integration with simulation-based flows.
• Collaborate closely with architecture, RTL, and design teams to identify corner cases, ensure functional correctness, and drive verification sign-off.

Qualifications:

• B.Sc. in Computer Science or Computer Engineering.
• 3+ years of industry experience in formal verification.
• Proven experience with JasperGold, VC Formal, or similar formal verification tools.
• Demonstrated ownership and maintenance of formal verification environments.
• Strong analytical and problem-solving skills.
• Team player with excellent interpersonal and communication abilities.
• English - Upper-Intermediate.

Advantages:

• Experience as a verification engineer with practical knowledge of SystemVerilog and UVM methodology.
• Familiarity with networking architectures and IPs (Switches, NICs, SmartNICs).
• Experience integrating formal verification within broader project verification flows.

We offer:

• 5-day working week, 8-hour working day, flexible schedule.
• No time tracker.
• Competitive salary.
• Work-life balance.
• Remote work.
• Standard social guarantees: annual leave, sick days.
• We understand the value of knowledge and training, so if you will find interesting and useful courses for yourself, we will pay for them.
• We value life and work time therefore all issues are resolved on the spot without unnecessary bureaucracy.

We design integrated circuits for consumer, medical and automotive markets. The majority of these designs are complex SoC/ASIC architectures that integrate IPs, such as ARM and RISC-V CPUs and peripherals, DSP cores, analog cells and other IPs with progressive technology nodes: 24, 10, 7,  3 nanometers.

In our daily work we constantly face challenges that requires out of box thinking. This makes our lives an interesting and challenging adventure. Such attitude permits creation of products full of features that often outperform market. We are constant learners, the same we expect from our new employees. Hence, we’d be happy to meet passionate and keen on learning, bright young individuals.

Below is a brief list of skills/knowledge that ideally suit our job profile. Still it’s not an issue if you don’t possess some of those. To our opinion the fundamental engineer’s skills are problem solving and ability to learn.

Desired knowledge you may possess:

• Good understanding of digital/analog electronics and semiconductors physics
• FPGA placement and routing using EDA tools
• Experience with PCB design using such tools such as OrCAD, Altium Designer or similar
• Basic knowledge of scripting languages such as Tcl, Python, Make
• Beginner’s level of English

Optional skills you may have:

• FPGA design using HDLs or schematics editor
• Embedded systems design using IDEs such as Keil, AtmelStudio, IAR

We offer:

• Part- or full-time employment, flexible schedule
• On-job training in our Kyiv office with high skilled professionals
• Potential growth in the direction of ASIC design
• Paid sick leave and vacation

We design integrated circuits for consumer, medical and automotive markets. The majority of these designs are complex SoC/ASIC architectures that integrate IPs, such as ARM and RISC-V CPUs and peripherals, DSP cores, analog cells and other IPs with progressive technology nodes: 14, 10, 8, 7 nanometers.

You will be responsible for digital logic design and verification. Besides, you'd be able to learn and improve related methodologies. Below is a brief list of skills/knowledge that ideally suit our job profile. Still it’s not an issue if you don’t possess some of those. To our opinion the fundamental engineer’s skills are analytical thinking and ability to learn.

Essential qualifications:

-Degree in Electronics or related fields

-Good understanding of digital electronics

-Experience with EDA tools (Xilinx, Mentor Graphics, Synopsys or similar)

-Beginner’s level of English or higher

Optional qualifications you may have:

-FPGA design using HDL (Verilog, VHDL) or schematics editor

-IC design verification using System Verilog

-CPU architecture knowledge, embedded SW development

We offer:

-Full-time employment, flexible schedule

-On-job training in our Kyiv office with high skilled professionals

-Potential growth in directions of ASIC/FPGA design

-Social benefits, modern and comfortable office facilities

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.

Job Description:

Are you in search for a new challenge? Are you equipped with forward looking spirit and experienced in digital design flows and tools? Design-for-Test (DFT) is a multi-disciplinary field of growing complexity which involves cooperation among multiple VLSI engineering skills, including design, architecture, verification, backend, timing, test, ATE and reliability and more. Take the opportunity and join us as a Senior DFT Engineer.

Presently we expand our Ukraine VLSI team. You'd be able to work on projects in one team with Ukrainian engineers. Our Senior stuff is open for knowledge sharing on a daily basis.

Your Role:

• DfT implementation inline with existing test methodology for advance process nodes;
• Perform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST;
• Closely work with physical design team to resolve timing constraints/issues;
• Verify DFT circuitry and interface with other components/IPs and debug timing simulation issues;
• Debug and improve important DfT KPIs: test coverage/pattern efficiency;
• Hierarchical retargeting;

• Silicon bring-up, diagnosis and support for physical failure analysis.

   

Desired Qualifications/Skills:

• 5+ years of hands-on experience with DFT and test flows with commercial EDA tools for large and complex SOCs;
• Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST/LBIST;
• Experience with one of the main EDAs providers: Synopsys DFT Complier, Tetramax, VCS, Tessent and Modus/Encounter tool suite;
• Experience in RTL simulation, synthesis, Linting, CDC and RDC checks, STA, DFT, quality metrics is a plus;
• Hands-on in Perl/Tcl/Python scripting;

• Excellent analytical, and problem-solving skills.

   

What you will love about working here?

• We care about all our employees and want them to feel as comfortable as possible. That's why we offer health insurance from the first days, regardless of the probationary period.
• The Gift from the Company - Christmas holidays from December 25 to December 31.

• Cooperation with Superhumans center and Veteran HUB. Capgemini Engineering has supported the launch of psychological rehabilitation department of Superhumans. Our team also donated over UAH 500 000 prosthetics for three Ukrainian defenders. Currently, we support psychological counseling provided by the Veteran Hub, and we have implemented an internal policy making the company friendly to military and veterans with the assistance of the Hub.

   

Capgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem.

Senior Design Verification Engineer
Your role:
• Own verification of IP’s and SoC’s in prototype and SoC design environment;
• Establish functional and performance benchmarks;
• Lead the definition, execution, and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms;
• IP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IP’s/SoC’s.
Your profile:
• Sound knowledge of SystemVerilog, and good experience in Constrained Random and Coverage Driven Verification with UVM/OVM
• Experience in creating any UVC components or sequences is a must
• Basic knowledge on at least two of these: AHB/AXI, PCIe/CXL, USB, DDR, Serial protocols, Processor Verification etc. Expertise in one protocol is a must for Senior and above.
• Should be comfortable in updating the existing verification environment for feature updates. (Bring-up/Architect UVM based Test bench from Scratch is a strong plus)
• EDA simulation/debugging tools agnostic.
• Good knowledge of Perl/TCL/Python scripting.
• Domain expertise on any one of these for senior and above: CPU processor/server, multimedia, automotive, Ethernet, Mobile
Our offer:
• Competitive Salary & Benefits;
• Knowledge and support from more experienced engineers;
• Respect for your private life and your choices;
• All tools required for high performance in your field;
• Responsible approach, long term commitments, and stability;

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.

Presently we expand our Ukraine VLSI team. You'd be able to work on projects in one team with Ukrainian engineers. Our Senior stuff is open for knowledge sharing on a daily basis.

Job Responsibilities:

• Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below);
• In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route;
• Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing);
• In charge with all validation/qualification tasks: Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes;
• Be part of the overall Low Power solution development and implementation;
• Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level);

• Complete multiple design cycles of high complexity with little supervision.

   

Desired Qualifications/Skills:

• 5+ years (desirable) in challenging RTL2GDSII work done on 10nm or below nodes with 500k – 1million+ instances in designs;
• Power user of PnR and timing analysis CAD tools from Synopsys and/or Cadence;
• Good knowledge of synthesis flow, insertDFT scan/coverage and optimization;
• Excellent floorplan, power plan, CTS, place, route, and timing closure skills;
• Proficiency using Perl/TCL/Python scripting and Makefile;
• Expertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation skill;
• Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills;
• Experience with sign-off tape-out closure work;

• Any top level – floor planning, pin assignment – tape out activities is a plus.

   

What you will love about working here?

• We care about all our employees and want them to feel as comfortable as possible. That's why we offer health insurance from the first days, regardless of the probationary period.
• The Gift from the Company - Christmas holidays from December 25 to December 31.
• Cooperation with Superhumans center and Veteran HUB. Capgemini Engineering has supported the launch of psychological rehabilitation department of Superhumans. Our team also donated over UAH 500 000 prosthetics for three Ukrainian defenders. Currently, we support psychological counseling provided by the Veteran Hub, and we have implemented an internal policy making the company friendly to military and veterans with the assistance of the Hub.

Capgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem.