FPGA Engineer

About the role

We’re looking for a hands-on FPGA engineer to design, simulate, and debug digital logic for high-performance embedded systems. You’ll work across Intel (Altera) and Xilinx device families, build robust interfaces to common peripherals, and help optimize datapaths for image/vision workloads.

What you’ll do

• Architect, implement, and integrate FPGA modules in VHDL/Verilog/SystemVerilog
• Target and maintain designs for Intel (Altera) and Xilinx FPGAs (Cyclone/Arria/Stratix; Artix/Kintex/Zynq)
• Create and run simulations (unit, module, and system-level) to verify functionality and timing before hardware bring-up
• Debug on hardware using built-in tools (Intel SignalTap, Xilinx Integrated Logic Analyzer/ChipScope), assertions, and testpoints
• Implement and validate standard interfaces: I²C, SPI, MIPI (D-PHY/CSI-2), and LVDS
• Handle timing closure: constraints (SDC/XDC), CDC, false/multicycle paths, floorplanning as needed
• Collaborate with firmware, hardware, and imaging teams to define requirements and deliver tested releases

What you’ll bring (must-have)

• 2+ years of FPGA development with both Intel (Altera) Quartus Prime and Xilinx Vivado toolchains
• Strong RTL design and verification skills; experience writing self-checking testbenches
• Proficiency with simulation tools (ModelSim/Questa, Vivado Simulator, etc.)
• Proven on-board debug using SignalTap and/or ILA
• Solid understanding of digital design fundamentals: pipelining, FIFOs, resets, clocking, PLLs/MMCMs, CDC
• Practical experience with I²C, SPI, MIPI, and LVDS at the register-transfer and constraint levels
• Version control (Git) and clean, reviewable code practices

Nice to have

• Image/video processing pipelines (ISP, scaling, filtering, HDR)
• External DDR(3/4/LPDDR) interfaces and memory controllers (Xilinx MIG, Intel EMIF): throughput budgeting, burst tuning, and arbitration
• High-speed links (MIPI CSI-2/DSI, SERDES, JESD/LVDS framing) and basic signal-integrity awareness
• Embedded SoC FPGAs (Zynq/Zynq UltraScale+, Intel SoC), AXI/AHB interconnects, and HW/SW co-design
• Scripting for build/test automation (Tcl, Python, Make/CMake)

Tools you’ll use

• Intel Quartus Prime, Platform Designer; Xilinx Vivado/Vitis
• ModelSim/Questa or Vivado Simulator
• SignalTap, ILA, timing analyzers, and constraint editors
• Git

Education

BSc/MSc in Electrical/Computer Engineering or equivalent practical experience.