Developing and packaging IP components for capturing and processing data from ethernet controllers. Porting algorithms from C/C++ to FPGA. Participating in bringing up interaction between FPGA Fabric and processor cores.

Writing verification test benches for developed modules. Making corrections in timing constraints files. Performing power, speed, and area optimizations.


- Bachelor's degree in computer engineering with strong theoretical background in the field or at least one year of proven commercial experience in modern FPGA design.

- Hands-on experience with one of the HDL languages (VHDL, Verilog, System Verilog). System Verilog will be a plus.

- Understanding the architecture of any modern FPGA (Xilinx or Intel) and basic timing constraints

- Basic experience with behavioral simulation using either VivadoSim, ModelSim or QuestaSim

- Ability to implement the basic digital circuits (registers, multiplexers, memory) at Register Transfer Level (RTL).

- Experience with IDE (Vivado or Quartus)

- Ability to read simple C/C++ code

- Git version control system


- AMBA AXI Interface understanding

- Hands-on experience with TCP/IP and UDP protocols

- Experience with JTAG/ILA debugging

- Experience with measurement hardware and soldering station

- C/C++ and Python programming skills

- Experience with Yocto Build System

Keywords: FPGA, VHDL, Verilog, System Verilog, Vivado

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Job posted on 23 June 2022
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